Monitor analogue output clock¶

A line at 240 Hz in the arterial pressure and plethysmogram (weakly in the ECG) runs −25 to −29 ppm against the SNUADC sample clock: most likely the patient monitor's output stage.

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Imported from the time-source table; the full page is still to be written.


Type	oscillator
Nominal	240 Hz line in the analogue outputs

Route to UTC¶

The route the atlas trusts most (3 links; its weakest link is estimated apart from the link to UTC that every clock shares):

Monitor analogue output clock

link estimated Monitor output clock against SNUADC: drift −25.4 to −28.7 ppm (6 cases)

SNUADC sample clock

link measured SNUADC (frequent-correction mode) against the recorder PC: drift −0.954 ppm (n = 6321; census of 6,321 files (17 October): median −0.9535 ppm; 89.5% of recording hours within 0.05 ppm of −0.954; 747 files (12%) between −0.90 and −0.55 ppm)

Recorder PC clock

link assumed Recorder PC against UTC: drift 0.1–10 ppm (assumed); corrected every 8–24 h (assumed)

UTC

Where every route ends.

Independent checks. 3 other routes reach UTC; where they meet, the offsets must close around the loop:

Plan. Measured against SNUADC on 6 files only. To strengthen: run the line scan on all cases, settle whether the line is 240 Hz or an aliased 260 Hz (which flips the sign), and match it to the PC-stamped Solar8000 numerics for a second route.

Links to other clocks¶

Link	Clock	Against	Modes	Rate	Corrected every	Status
Monitor output clock against SNUADC	Monitor analogue output clock	SNUADC sample clock	all	−25.4 to −28.7 ppm (6 cases)	—	estimated

Parameters¶

Parameter	Value	Status	From
Monitor 240 Hz line against SNUADC	−25.4 to −28.7 ppm (6 cases)	measured	Monitor clocks in the waveforms' spectral lines

Studies¶

Study	Date	Status	Summary
Monitor clocks in the waveforms' spectral lines	2026-10-17	open	Differences of the raw converter counts show lines from the monitor's analogue outputs: 240 Hz in arterial pressure and plethysmogram, and a 30 Hz family in the plethysmogram alone. Each measures a monitor clock against SNUADC.
The SNUADC firmware	2026-10-13	current	The public SNUADC firmware explains the board's timing: it sends no time stamps, samples on its 16 MHz crystal, loses time rather than bunching samples after a stall, reads its channels one after another, and truncates its values. A predicted fault at the microsecond counter's wrap was not found in the data.

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